High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (e.g., dies) vertically and interconnecting the chips using through substrate vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface chip and vertically stacked DRAM chips. A typical HBM stack of four DRAM chips (e.g., core chips) has two 128-bit channels per chip for a total of eight input/output channels and a width of 1024 bits in total. An interface (IF) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. In the HBM, data transmission between chips (e.g., between an interface chip and core chips) via through substrate vias (TSVs) may cause high power consumption, due to current charge and discharge at the TSVs as capacitors.
3D memory devices (e.g., HBM and the like) support data bus inversion during write and read operation for reducing currents in data transmission between a host controller and chips (e.g., dies). As shown in FIG. 1A, a data bus inversion (“DBT”) encoder in a 3D memory device encodes write data using a DBI algorithm and transmits DBI bit or bits indicating whether the write data from a host device to a memory device chip have been inverted. The DBI encoder compares current data bits Di on a data bus with previous data bits Dn-1 on the data bus and minimizes a number of data bits that simultaneously transition between the previous data bits and the current data bits by transmitting the data bits Do after inversion when the number of data bits that simultaneously transition is more than half of the number of the data bits, as shown in FIG. 1B. Thus, the data bus inversion decreases a number of data bits with transition on the data bus and reduces currents due to transition of the data bits. In order to signal whether the data inversion has been applied, one DBI bit DBIo is added to the data bits. The DBI encoding operation is activated responsive to the assertion of a DBI enable signal EN. In case of the 3D memory devices with a plurality of dies having a number of TSVs for data transmissions between the plurality of dies, a number of DBI bits to support DBI increases and the number of TSVs increases accordingly. The output data bits Do and the DBI bit DBIo from the DBI encoder in FIG. 1A are supplied to a DBI decoder as input data bits Do and input DBI bit DBIi as shown in FIG. 2A, so that the encoded DBI bits are decoded to the original data bits as shown in FIG. 2B. The DBI decoding operation is also activated responsive to the assertion of the DBI enable signal commonly provided to the DBI encoder and the DBI decoder.
In a 3D memory device, on the other hand, there may be defects in connection (e.g., TSVs), such as improper connections to adjacent wirings, open terminals with high impedance due to poor connection, high resistance due to contamination, in TSVs for transmitting data between adjacent dies stacked to each other. This type of defects in connections may exacerbate a yield of devices. In order to enhance the yield of devices, a redundant TSV and a domino circuit are provided in each die, as shown in FIG. 3. The detailed operations of the domino circuit using the redundant TSV will be omitted as being well known in the art.